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Architecture Overview
DMA BUS
PMB
Interface
GDB BUS
Y Memory
Control
Logic
FDIR
4-Word
Data Input Buffer
FCNT
Filter Count
FCBA
Shared
RAM
FCM
Coeff. Base Ad.
X Memory
Shared
RAM
FKIR
Filter Constant
FDM
DATA
Memory Bank
24-bit
FDBA
Data Base Ad.
Address
Generator
FMAC
24x24 -> 56-bit
COEFFICIENT
Memory Bank
24-bit
Rounding & Limiting
Output Buffer
FDOR
Figure 10-1. EFCOP Block Diagram
10.2.1 PMB Interface
The PMB interface block contains control and status registers, buffers the internal bus from the
PMB, decodes and generates addresses, and controls the handshake signals required for DMA
and interrupt operations. The block generates interrupt and DMA trigger signals for data
transfers. The interface registers accessible to the DSP56300 core through the PMB are
summarized in Table 10-1 .
Table 10-1. EFCOP Registers Accessible Through the PMB
Register Name
Filter Data Input Register
(FDIR)
Filter Data Output
Register (FDOR)
Filter K-Constant Input
Register (FKIR)
Filter Count (FCNT)
Register
EFCOP Control Status
Register (FCSR)
Freescale Semiconductor
Description
A 4-word-deep 24-bit-wide FIFO used for DSP-to-EFCOP data transfers. Data from the FDIR is
transferred to the FDM for filter processing.
A 24-bit-wide register used for EFCOP-to-DSP data transfers. Data is transferred to FDOR
after processing of all filter taps is completed for a specific set of input samples.
A 24-bit register for DSP-to-EFCOP constant transfers.
A 24-bit register that specifies the number of filter taps. The count stored in the FCNT register
is used by the EFCOP address generation logic to generate correct addressing to the FDM and
FCM.
A 24-bit read/write register used by the DSP56300 core to program the EFCOP and to examine
the status of the EFCOP module.
DSP56311 Reference Manual, Rev. 2
10-3
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